In semiconductor fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces, forming devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC). The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization. Such techniques are described in S. M. Sze, VLSI Technology, 2nd ed., New York, McGraw-Hill, 1988, which is herein incorporated by reference for all purposes.
To increase throughput, a plurality of ICs are fabricated on a wafer in parallel. The ICs are then separated into individual chips. The process of separating the wafer into individual chips is typically referred to as "dicing." Conventionally, various dicing techniques, such as "grind-cut" and "scribe and break", are employed. Such conventional dicing techniques are described in U.S. Pat. No. 3,942,508 to Shimizo, which is herein incorporated by reference for all purposes.
Referring to FIG. 1, a portion of a wafer 100 is depicted. Illustratively, the wafer comprises ICs 114 and 115 separated by a channel 120. Channel 120 is the area in which the dicing tool cuts or scribes to separate the ICs. The width of the channel is, for example, about 100 microns (.mu.m). Typically, the channel is covered with a dielectric layer 121, such as oxide. The surface of the wafer is covered with hard and soft passivation layers 124 and 125, respectively. The hard passivation layer, for example, comprises silicon dioxide or silicon nitride and the soft passivation layer comprises polymide. The passivation layers serve to protect the surface of the ICs. Prior to wafer dicing, the passivation layers in the channel are typically removed, leaving a portion of the dielectric layer of the metallization.
As the dicing tool cuts or scribes the wafer, cracks and chips result. Due to the properties of the typical dielectric layer, cracks propagate from the area where the dicing tool cuts the wafer. Cracks in excess of a few microns in depth and several tenths of millimeters in length have been observed. In some instances, such cracks can extend from the cutting edge into the active chip areas, causing significant reliability degradation in the resulting ICs. This decreases the yield of ICs per wafer.
From the above discussion, it is apparent that there is a need to reduce the propagation of cracks and chips that result from dicing.